Clock selection circuits are old and well known. A recent development in the state of this art was disclosed in U.S. Pat. No. 4,322,580 which issued on Mar. 30, 1982. The clock selection circuit disclosed therein scans a plurality of available clock circuits upon detection of failure of an on-line clock circuit, and places another properly operating clock circuit on-line. One feature of that circuit is that it scans through the various clock circuits in a certain sequence to select the next properly operating clock circuit. However, that circuit may fail to complete its scan and a new clock circuit will not be selected if certain logic gates in the scanning circuitry fail.
The present invention discloses a novel arrangement for selecting a clock circuit and this new arrangement has a greater tolerance to logic gate failures than the arrangement disclosed in the referenced patent.